/*
* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/

#ifndef BSP_CLOCK_CFG_H_
#define BSP_CLOCK_CFG_H_
#define BSP_CFG_CLOCKS_SECURE (0)
#define BSP_CFG_CLOCKS_OVERRIDE (0)
#define BSP_CFG_CLOCK_OSCCLK_HZ (24000000) /* OSC 24000000Hz */
#define BSP_CFG_CLOCK_PLL1_HZ (1000000000) /* PLL1 1000000000Hz */
#define BSP_CFG_DIVPL1_SET_DIV (BSP_CLOCKS_PL1_DIV_1) /* ICLK Div /1 */
#define BSP_CFG_CLOCK_ICLK_HZ (1000000000) /* ICLK 1000000000Hz */
#define BSP_CFG_CLOCK_PLL2_1600_HZ (1600000000) /* PLL2 1600000000Hz */
#define BSP_CFG_CLOCK_PLL2_533_HZ (533000000) /* PLL2 533000000Hz */
#define BSP_CFG_SEL_SDHI0_SET_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2_400) /* SD0CLK Sel: 400MHz */
#define BSP_CFG_CLOCK_SD0CLK_HZ (400000000) /* SD0CLK 400000000Hz */
#define BSP_CFG_SEL_SDHI1_SET_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2_400) /* SD1CLK Sel: 400MHz */
#define BSP_CFG_CLOCK_SD1CLK_HZ (400000000) /* SD1CLK 400000000Hz */
#define BSP_CFG_DIVPL2A_SET_DIV (BSP_CLOCKS_PL2A_DIV_1) /* P0CLK Div /1 */
#define BSP_CFG_CLOCK_P0CLK_HZ (100000000) /* P0CLK 100000000Hz */
#define BSP_CFG_CLOCK_TSUCLK_HZ (80000000) /* TSUCLK 80000000Hz */
#define BSP_CFG_CLOCK_PLL3_1600_HZ (1600000000) /* PLL3 1600000000Hz */
#define BSP_CFG_CLOCK_ATCLK_HZ (400000000) /* ATCLK 400000000Hz */
#define BSP_CFG_DIVPL3CLK200FIX_SET_DIV (BSP_CLOCKS_PL3CLK200FIX_DIV_1) /* I2CLK Div /1 */
#define BSP_CFG_CLOCK_I2CLK_HZ (200000000) /* I2CLK 200000000Hz */
#define BSP_CFG_DIVPL3B_SET_DIV (BSP_CLOCKS_PL3B_DIV_1) /* P1CLK Div /1 */
#define BSP_CFG_CLOCK_P1CLK_HZ (200000000) /* P1CLK 200000000Hz */
#define BSP_CFG_CLOCK_M0CLK_HZ (200000000) /* M0CLK 200000000Hz */
#define BSP_CFG_CLOCK_ZTCLK_HZ (100000000) /* ZTCLK 100000000Hz */
#define BSP_CFG_DIVPL3A_SET_DIV (BSP_CLOCKS_PL3A_DIV_1) /* P2CLK Div /1 */
#define BSP_CFG_CLOCK_P2CLK_HZ (100000000) /* P2CLK 100000000Hz */
#define BSP_CFG_CLOCK_PLL3_533_HZ (533000000) /* PLL3 533000000Hz */
#define BSP_CFG_SEL_PLL3_3_SET_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL3_533) /* PLL3_3 Sel: 533MHz */
#define BSP_CFG_DIVPL3C_SET_DIV (BSP_CLOCKS_PL3C_DIV_2) /* PLL3_3 Div /2 */
#define BSP_CFG_CLOCK_SPI0CLK_HZ (133250000) /* SPI0CLK 133250000Hz */
#define BSP_CFG_CLOCK_SPI_QSPI0_SPCLK_HZ (66625000) /* SPI QSPI0_SPCLK 66625000Hz */
#define BSP_CFG_CLOCK_PLL3_400_HZ (400000000) /* PLL3 400000000Hz */
#define BSP_CFG_CLOCK_SPI1CLK_HZ (66625000) /* SPI1CLK 66625000Hz */
#define BSP_CFG_CLOCK_M2CLK_HZ (266500000) /* M2CLK 266500000Hz */
#define BSP_CFG_SEL_PLL3_5_SET_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL3_400) /* PLL3_5 Sel: 400MHz */
#define BSP_CFG_DIVPL3F_SET_DIV (BSP_CLOCKS_PL3F_DIV_1) /* PLL3_5 Div /1 */
#define BSP_CFG_CLOCK_OC0CLK_HZ (200000000) /* OC0CLK 200000000Hz */
#define BSP_CFG_CLOCK_OCTA_QSPI0_SPCLK_HZ (100000000) /* Octa QSPI0_SPCLK 100000000Hz */
#define BSP_CFG_CLOCK_OC1CLK_HZ (100000000) /* OC1CLK 100000000Hz */
#define BSP_CFG_CLOCK_PLL4_HZ (1600000000) /* PLL4 1600MHz */
#define BSP_CFG_SEL_PLL4_SET_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL4_1600) /* Sel: PLL4 */
#define BSP_CFG_CLOCK_S0CLK_HZ (800000000) /* S0CLK 800000000Hz */
#define BSP_CFG_CLOCK_PLL5_1500_HZ (1500000000) /* PLL5 1500000000Hz */
#define BSP_CFG_DIVDSIA_SET_DIV (BSP_CLOCKS_DSIA_DIV_2) /* DSI_A Div /2 */
#define BSP_CFG_DIVDSIB_SET_DIV (BSP_CLOCKS_DSIB_DIV_1) /* DSI_B Div /1 */
#define BSP_CFG_CLOCK_M3CLK_HZ (750000000) /* M3CLK 750000000Hz */
#define BSP_CFG_CLOCK_PLL5_500_HZ (500000000) /* PLL5 500000000Hz */
#define BSP_CFG_CLOCK_PLL6_HZ (500000000) /* PLL6 500000000Hz */
#define BSP_CFG_SEL_PLL6_2_SET_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL6_250) /* PLL6_2 Sel: 250MHz (from PLL6) */
#define BSP_CFG_CLOCK_HPCLK_HZ (250000000) /* HPCLK 250000000Hz */
#endif /* BSP_CLOCK_CFG_H_ */
